JESD51-10 Test Boards for Through-Hole Perimeter Leaded Package Thermal

  
jesd51-10 Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.pdf

Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
JESD51-10
JULY 2000

CONTENTS

1 Scope 1
2 Normative references 1
3 Stock material 2
4 Board outline 3
5 Trace design 4
5.1 Top trace layer layout (both 1s and 2s2p PCBs) 4
5.2 Trace widths for 1s and 2s2p PCBs 6
5.3 Plated through-hole vias 6
5.4 Thermal pins (2s2p only) 7
5.5 Trace layers and connection routing 7
5.6 Buried layer layout (2s2p PCB only) 7
5.7 PCB metalization characteristics for 1s and 2s2p PCBs 8
5.8 Solder masks for 1s and 2s2p PCBs 8
6 Hand wiring 8
7 Data presentation 10
Tables
1 PCB sizes for packages 3
2 PCB buried plane sizes 7
3 Wire size current limits 8
4 Specified parameters and values used 10
Figures
1a Cross section of 1s PCB showing trace and dielectric thicknesses in package placement 2
and trace fan-out regions
1b Cross section of 2s2p PCB showing trace and dielectric thicknesses 2
2 Example test board outer dimensions and edge connector design 3
3 Traces flared to perimeter 25 mm from package body 4
4 Nested design with traces flared to perimeter 25 mm from largest package body 5
5 Traces flared to perimeter 25 mm form SIP body 5
6 Hand wiring test board suggestion 9

1 Scope
This specification covers through-hole mount perimeter leaded packages intended to be mounted on a PCB. It does not cover area array packages that require sockets or PGA packages.

zz

還不知道這東西也能DIY。

有意思，有機會可以玩玩，可以給自己的DC/DV裝個投影儀~