EIA/JESD51-4 Thermal Test Chip Guideline

jesd51-4 Thermal Test Chip Guideline (Wire Bond Type Chip).pdf


1 Introduction
1.1 Purpose
1.2 Scope
1.3 Rationale
1.4 References
2 Test Chip Design
2.1 Heating Source
2.2 Temperature Sensor
2.3 Bonding Pads
2.4 Physical Layout
2.4.1 Chip Dimensions
2.4.2 Heating Source Area Coverage
2.4.3 Temperature Sensor Placement
2.4.4 Wire Bonding Considerations
2.5 Surface Properties
3 Data Presentation

1 Introduction
(From JEDEC Council Ballot JCB-96-25 formulated under the cognizance of JC-15.1 Committee on Thermal Characterization).
1.1 Purpose
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) package thermal characterization. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips.
1.2 Scope
The thermal test chips described in this document will apply to single and multiple chip devices. These are designs using standard semiconductor wafer fabrication processes and can be used with a wide variety of industry standard packages. These test chips can operate in a static mode in which constant power is continuously supplied to the device while monitoring the temperature through the measurement of a Temperature Sensitive Parameter (TSP). They can also operate in a transient mode in which the power supply and the TSP are monitored as a function of time (t). This guideline covers test chips meant to be wire bonded to the package external leads.